Anti-Tamper Digital Clocks - An Overview
Anti-Tamper Digital Clocks - An Overview
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3. The method for detecting clock tampering as described in claim one, whereby using the clock to set off the Appraise circuit comprises utilizing a clock edge at an conclusion with the clock evaluate time period to result in the Consider circuit.
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The methods of a method or algorithm explained in connection with the embodiments disclosed herein could be embodied specifically in components, or in a combination of hardware as well as a computer software module executed by a processor. A computer software module may perhaps reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, tricky disk, a removable disk, a CD-ROM, or some other form of storage medium regarded from the art.
Resettable hold off line segments between a resettable hold off line section linked to a minimum hold off time along with a resettable hold off line section linked to a utmost delay time are Just about every connected with discretely growing delay occasions. The Consider circuit is brought on with the clock and employs the plurality of delayed monotone alerts to detect a clock fault.
37. An equipment for detecting voltage tampering, comprising: a circuit that provides a monotone signal throughout an Examine time period;
34. The apparatus for detecting voltage tampering as outlined in assert 33, wherein the water level amount is determined determined by delayed monotone alerts from a number of former evaluate time.
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A different element of the creation may perhaps reside within an equipment for detecting clock tampering, comprising: means for providing a monotone signal throughout a clock Appraise period of time linked to a clock; implies for delaying the monotone signal employing a plurality of resettable delay line segments to deliver a respective plurality of delayed monotone signals owning discretely rising hold off times concerning a minimum delay time plus a utmost delay time; and signifies for utilizing the clock to bring about an Consider circuit that employs the plurality of delayed monotone indicators to detect a clock fault.